Steps for initilization floor plan and assignment of pins in Synopsys IC Compiler 2

Steps for initilization floor plan and assignment of pins in Synopsys IC Compiler 2

1. Define attributes for horizontal and vertical metal layers

         set_attribute [get_layers {M2 M4 M6 M8 AP} ] routing_direction vertical
         set_attribute [get_layers {M1 M3 M5 M7 M9} ] routing_direction horizontal          
         #Odd metal layers are horizontal and even metal layers in vertical direction

2. Define Die area and core area

          initialize_floorplan -core_utilization 0.6 -core_offset {2 2 2 2}
          #The die is defined for 60% utilization and core boundary  with an offset of 2 in all the four 
          #sides from die offset are for {left top right bottom}
          # Standard cell utilization = Total_std_cell_area / Placement_area
          # This should be 60% to 65%
          # Core_offset = die_boundary - core_boundary


3. Create a pin guide in the current design
   
           create_pin_guide -layers {M3 M5} -boundary { {38 0.4} {39.14 39}} [get_ports *]
           # This pin guide is used for placing the pins in the die boundary 
           # If pins are placed in top or bottom then it is recommended to use vertical  {M4 M6} layers
           # If pins are placed in left or right then it is recommended to use vertical  {M3 M5} layers

4. Placing pins on blocks within current design or current block

           place_pins -self


5. save this as a block for later references

           save_block -as block_name
           # save_block as myALU_pin_placed

******************************************************************************
            Purple color indicates the step to include
            Brown_clour indicates the command for the corresponding step
            Blue_clour indicates comment given as example 
 ******************************************************************************