Steps for power planning in Synopsys IC Compiler 2

Steps for power planning in Synopsys IC Compiler 2

1. Create nets for VDD and VSS and its top level ports

         create_net -power vdd
         create_net -ground gnd

         create_port -direction in -port_type power vdd
         create_port -direction in -port_type gnd  gnd          


2. Connect Power, Ground to the specified power

          connect_pg_net -net vdd [get_ports vdd]
          connect_pg_net -net vss [get_ports vss]

          connect_pg_net -net vdd [get_flat_pins -all *VDD]
          connect_pg_net -net gnd [get_flat_pins -all *VSS]
 
3. Create a standard cell rail connection pattern . This pattern can be initiated in a design by set_pg_strategy command to create standard cell rails
   
           create_pg_std_cell_conn_pattern rail_pattern -layers M1
           set_pg_strategy M1_rails -core -pattern { {name: rail_pattern} {nets: vdd gnd} }
           # Here the pattern and strategy names are rail_pattern and M1_rails these are users choice
           # For standard cell the M1 layer is used for power rails which will lie on site rows
           # The vdd and gnd rails are placed equal in number. 
           # usually preferred rail pattern is vdd gnd vdd gnd ......

4. Create a power, ground mesh pattern and instantiated in a design by set_pg_strategy to create power, ground mesh

           create_pg_mesh_pattern m2tom7_mesh_pattern \
            - layers { \
                        {vertical_layer: M2} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}} \
                        {vertical_layer: M3} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}} \
                        {vertical_layer: M4} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}} \
                        {vertical_layer: M5} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}} \
                        {vertical_layer: M6} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}} \
                        {vertical_layer: M7} {width: 0.1} {spacing: minimum} {pitch: 4.14} {offset: 0.27}}\ 
                        }

           set_pg_strategy PG_mesh -core -pattern {{name: m2tom7_mesh_pattern} {nets: vdd gnd }} \                                            -extension {{layers: M2} {stop: 0.2} }
          
5. Create a power, ground mesh pattern and instantiated in a design by set_pg_strategy to create power, ground mesh ( Top power rails usually M8, M9}

           create_pg_mesh_pattern m8m9_mesh_pattern \
            - layers { \
                        {vertical_layer: M8}     {width: 1.0} {spacing: minimum} {pitch: 6.0} {offset: 1.4}} \
                        {horizontal_layer: M9} {width: 1.0} {spacing: minimum} {pitch: 3.0} {offset: 0.9}} \
                        }

           set_pg_strategy M8M9PG_mesh -design_boundary -pattern {{name: m8tom9_mesh_pattern} {nets: vdd gnd }} \
                                                    -extension {{stop: design_boundary_and_generate_pin} }



6. Compile PG strategies

           compile_pg -strategies {strategies_name}
           # compile individual strategies after each strategy    compile_pg_strategies {M1_rails}   or
           # compile multiple strategies after each strategy    compile_pg_strategies {M8M9PG_mesh PG_mesh M1_rails} 

7. save this as a block for later references

           save_block -as block_name
           # save_block as myALU_power_plan

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            Purple color indicates the step to include
            Brown_clour indicates the command for the corresponding step
            Blue_clour indicates comment given as example 

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