Steps for initialization of libraries and net-list in Synopsys IC Compiler 2
1. Create technology libraries and reference libs
set NDM_LIB { tcbn28hpcplusbwp40p140lvt_c.ndm \
tcbn28hpcplusbwp40p140hvt_c.ndm\
tcbn28hpcplusbwp40p140_c.ndm }
set TECH_LIB tsmcn28_9lm4X2Y2RUTRDL.tf
set search_path "/home/..../lvt28/ndm /home/..../hvt28/ndm /home/..../svt28/ndm \
/home/..../tech/tech_file_path /home/user3 \
/ICC2/inputs_file_path_for_sdc_and_netlist"
create_lib -ref_libs $NDM_LIB -technology $TECH_LIB my_own_lib_name.ndm
# create_lib -ref_libs $NDM_LIB -technology $TECH_LIB myALU.ndm
2. Read Verilog file after synthesis i.e netlist file
read_verilog -top top_module_name syn_verilog_file.vg
#read_verilog -top myALU map_hdl.vg
3. Link verilog net list to tech and ref libraries
link
4. save our own libraries
save_lib
5. save this as a block for later references
save_block -as block_name
# save_block as myALU_Init
******************************************************************************
Purple color indicates the step to include
Brown_clour indicates the command for the corresponding step
Blue_clour indicates comment given as example
******************************************************************************
1. Create technology libraries and reference libs
set NDM_LIB { tcbn28hpcplusbwp40p140lvt_c.ndm \
tcbn28hpcplusbwp40p140hvt_c.ndm\
tcbn28hpcplusbwp40p140_c.ndm }
set TECH_LIB tsmcn28_9lm4X2Y2RUTRDL.tf
set search_path "/home/..../lvt28/ndm /home/..../hvt28/ndm /home/..../svt28/ndm \
/home/..../tech/tech_file_path /home/user3 \
/ICC2/inputs_file_path_for_sdc_and_netlist"
create_lib -ref_libs $NDM_LIB -technology $TECH_LIB my_own_lib_name.ndm
# create_lib -ref_libs $NDM_LIB -technology $TECH_LIB myALU.ndm
2. Read Verilog file after synthesis i.e netlist file
read_verilog -top top_module_name syn_verilog_file.vg
#read_verilog -top myALU map_hdl.vg
3. Link verilog net list to tech and ref libraries
link
4. save our own libraries
save_lib
5. save this as a block for later references
save_block -as block_name
# save_block as myALU_Init
******************************************************************************
Purple color indicates the step to include
Brown_clour indicates the command for the corresponding step
Blue_clour indicates comment given as example
******************************************************************************
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