Synthesize
using Design Compiler
Invoking Design Compiler
1>
Shell Version
v
> dc_shell |tee log_file.txt
2>
GUI Version (Design Vision)
v
>gui_start // from shell
Sequence of steps
(Synthesis stages and Commands)
1)
Load tech libraries into database (Click_here_for_example)
o target_library
o link_library
o symbol_library
o synthetic_library
2) Read Design (HDL), Analyse and Elaborate Design (Click_here_for_example)
o analyse
o elaborate
o read_files
3) Define Design environment parameters (Click_here_for_example)
o set_operating_conditions
o set_wire_load_model
o set_drive
o set_driving_cell
o set_load
o set_fanout_load
o set_min_library
4) Specify Design rules / Constraints (Click_here_for_example)
o set_max_transition
o set_max_fanout
o set_max_capacitance
5)
Design Optimization constraints (Click_here_for_example)
o create_clock
o set_clock_latency
o set_propagated_clock
o set_clock_uncertainty
o set_clock_transition
o set_input_delay
o set_output_delay
o set_max_area
6) Compile and optimize Design (Repeat if necessary) (Click_here_for_example)
o compile
o compile_ultra
7)
Generate netlist and reports (Click_here_for_example)
o check_design
o report_area
o report_constraint
o report_timing
8) Save the design database (Click_here_for_example)
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