LIBRARY
IEEE;
USE
IEEE.STD_LOGIC_1164.ALL;
ENTITY
SEQ_101010 IS
PORT
(CLK, RST_L, SIN: IN STD_LOGIC;
DET : OUT STD_LOGIC);
END
SEQ_101010;
ARCHITECTURE
ARCH1 OF SEQ_101010 IS
TYPE STATE IS
IN (S0, S1, S2, S3, S4, S5, S6);
SIGNAL PRE_STATE, NXT_STATE : STATE;
BEGIN
PROCESS (CLK)
BEGIN
IF CLK’EVENT AND CLK = ‘1’
THEN
IF RST_L = ‘0’ THEN PRE_STATE <= S0;
ELSE PRE_STATE
<= NXT_STATE;
END IF;
END IF;
END PROCESS;
PROCESS (PRE_STATE, SIN)
BEGIN
DET <= ‘0’;
CASE (PRE_STATE) IS
WHEN S0: IF SIN THEN NXT_STATE <= S1;
ELSE
NXT_STATE <= S0;
END
IF;
WHEN S1: IF SIN = ‘0’ THEN NXT_STATE <= S2;
ELSE
NXT_STATE <= S1;
END
IF;
WHEN S2: IF SIN THEN NXT_STATE <= S3;
ELSE
NXT_STATE <= S0;
END
IF;
WHEN S3: IF SIN THEN NXT_STATE <= S1;
ELSE
NXT_STATE <= S4;
END
IF;
WHEN S4: IF SIN THEN NXT_STATE <= S5;
ELSE
NXT_STATE <= S0;
END
IF;
WHEN S5: IF SIN THEN NXT_STATE <= S1;
ELSE
NXT_STATE <= S6;
END
IF;
WHEN S6: DET <= ‘1’;
END CASE;
END PROCESS;
END ARCH1;
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