create_clock

create_clk  -name  SYSCLK  -period 10 –waveform {0 5}  [get_ports clk]   

SYSCLK is the user defined clock name for the clock input “clk” in the design

-period specifies the clock period of “clk”. Here 10 indicates the clock period of clk signal

-waveform defined the duty cycle of the “clk” signal. Here 0-5 period clock will be at logic 1 and from 5-10 period the clock “clk” will be at logic 0.

Duty Cycle = Tclk_on / Tclk_period

get_ports  fetches the ports the signal of the design with name “clk”