VHDL Program for Ripple Carry Adder

VHDL Program for Ripple Carry Adder

library IEEE;

use IEEE.std_logic_1164.all;

entity RCA is

                port(A, B:    in         std_logic_vector(7 downto 0);

                         Cin :     in         std_logic;

                         Sum:    out       std_logic_vector(3 downto 0)

                         Cout :   out       std_logic);

end RCA;

architecture arch1 of RCA is

            signal C1, C2, C3 : std_logic;

            component FA port (A, B, Cin : in std_logic; Sum, Cout : out std_logic);

            end component;

begin

            u0: FA port map(A[0], B[0], Cin, Sum[0], C1);

            u1: FA port map(A[1], B[1], C1, Sum[1], C2);

            u2: FA port map(A[2], B[2], C2, Sum[2], C3);

            u3: FA port map(A[3], B[3], C3, Sum[3], Cout);

end arch1;