VHDL Program for Carry Look Ahead Adder in Structural Model

VHDL Program for Carry Look Ahead Adder in structural Model

library IEEE;

use IEEE.std_logic_1164.all;

entity CLA is

                port( A, B:    in         std_logic_vector(7 downto 0);

                          Cin :     in         std_logic;

                          Sum:    out       std_logic_vector(3 downto 0)

   Cout :   out       std_logic);

end CLA;

architecture arch1 of CLA is

            signal C1, C2, C3 : std_logic;

            signal x1, x2, x3 : std_logic;

            component FA port (A, B, Cin : in std_logic; Sum, Cout: out std_logic);

            end component;

            component C1_gen port (A0, B0, Cin: in std _logic; C1: out std_logic);

            end component;

            component C2_gen port (A0, A1, B0, B1, Cin: in std _logic; C2: out std_logic);

            end component;

            component C3_gen port (A0, A1, A2, B0, B1, B2, Cin: in std _logic; C3: out std_logic);

            end component;

begin

           

            u0: C1_gen port map (A[0], B[0], Cin, C1);

            u1: C2_gen port map (A[0], A[1], B[0], B[1], Cin, C2);

            u2: C3_gen port (A[0], A[1], A[2], B[0], B[1], B[2], Cin, C3);      

            u3: FA port map(A[0], B[0], Cin, Sum[0], x1);

            u4: FA port map(A[1], B[1], C1, Sum[1], x2);

            u5: FA port map(A[2], B[2], C2, Sum[2], x3);

            u6: FA port map(A[3], B[3], C3, Sum[3], Cout);

end arch1;