VHDL Program for Carry Look Ahead Adder using simple signal assignment

VHDL Program for Carry Look Ahead Adder using simple signal assignment

library IEEE;

use IEEE.std_logic_1164.all;

entity CLA is

                port( A, B:     in        std_logic_vector(7 downto 0);

                          Cin :     in         std_logic;

                          Sum:    out      std_logic_vector(3 downto 0)
                          Cout :    out     std_logic);

end CLA;

architecture arch1 of CLA is

            signal C1, C2, C3 : std_logic;

begin

           

            C1 <= (A[0] and B[0]) or ((A[0] xor B[0]) and Cin);

            C2 <=  (A[1] and B[1]) or ((A[1] xor B[1]) and ((A[0] and B[0]) or

((A[0] xor B[0]) and Cin)));

C3 <=  (A[2] and B[2]) or ((A[2] xor B[2]) and ((A[1] and B[1]) or ((A[1] xor B[1]) and

((A[0] and B[0]) or ((A[0] xor B[0]) and Cin)))));

            Sum[0]   <=   A[0] xor B[0] xor Cin;

            Sum[1]   <=    A[1] xor B[1] xor C1;

            Sum[2]   <=   A[2] xor B[2] xor C2;

            Sum[3]   <=   A[3] xor B[3] xor C3;

            Cout        <=   (A[3] and B[3]) or (B[3] and C3) or (A[3] and C3);

end arch1;