Verilog_Program_for_ALU

***********************************************************************************************

Design of ALU to Perform – ADD, SUB, AND, OR, 1’s compliment, 2’s Compliment, Multiplication and Division 

 Verilog Module

module  ALU_8BIT(A, B, OPR, RESULT);

          input [7:0] A, B;

          input [2:0] OPR;

          output [15:0] RESULT;

          reg [15:0] RESULT;

                   always@(OPR, A, B)

                   begin

                        case(OPR)

                             3’b000:   Y = A + B;

                             3’b001:   Y = A - B;

3’b010:   Y = A & B;

3’b011:   Y = A | B;

3’b100:   Y =  ~A ;

3’b101:   Y = ~A + 1;

3’b110:   Y = A * B;

3’b111:   Y = A / B;

default:  Y = 4’b0000;

                   endcase

          end

endmodule

Test Bench

module  TB_ALU_8BIT;

          reg [7:0] A, B;

          reg [2:0] OPR;

          wire [15:0] RESULT;

          initial

          begin

                   OPR = 0;

                   A = 10101010;

                   B = 01010101;

          end

          always

          #5 OPR = OPR + 1;

endmodule

***********************************************************************************