Verilog_Module_for_a_sequence_detector

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Verilog Module for a sequence detector to detect the sequence 1101

 Verilog Module

module seqdet(din, rst_l , clk, dout);

input din, clk, rst_l;

output dout;

//output [2:0]state;

reg [2:0] state, next_state;

reg dout;

parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;

always@(posedge clk)

          if (!rst_l)       state = s0;

          else              state = next_state;

always@(state)

begin

     case(state)

s0:     dout = 0;

s1:     dout = 0;

s2:     dout = 0;

s3:     dout = 0;

s4:     dout = 1;

     endcase

end

always@(posedge clk)

begin

     case(state)

s0:     next_state = din? s1 : s0;

s1:     next_state = din? s2 : s0;

s2:     next_state = din? s2 : s3;

s3:     next_state = din? s4 : s0;

s4:     next_state =  s0;

     endcase

end

endmodule

Test Bench

module tb_seqdet;

reg din, clk, rst_l;

wire dout;

          seqdet(din, rst_l , clk, dout);

          initial

          begin

                   clk = 0;

                   rst_l = 1;

                   #5 rst_l = 0;

                   #5 rst_l = 1;

                   #100  $stop;

          end

          always

          begin

                   #1 din = !din;

                   #1 din = 1;

#1 din = 1;

#1 din = 0;

#1 din = 1;

                   #5 din = !din;

          end

          always    #2    clk = !clk;

endmodule

  

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