Cadence_schematic_editor_steps

csh

source /cad/cshrc                                            --- Directs to Cadence Tool Suite

For Analog designs -- Commands

# virtuoso

            Opens two windows     1. overview  (you can close)

                                                2. logfile   --  cds.log

In CDS.log

For creating library

1. click tools --> Library Manager  option

2. In library manager

            file  -->  new  -->  Library

3. In new library

            Name (Specify new library name (one time only))  --- >  OK  --->  select attach to an                        existing technology library  -->  OK      --->  select gpdk180   -->  ok

                        ( You can see your library under library window)

To create a schematic

4. click myDesign in Library coln then file --> new --> cellview 

            specify  cell name     inverter (view  schematic)  --> ok  -->  select always

5. in schematic view  --> create instance (or) press i

For placing transistors

            in add instance window

               browse gpdk180   library (select it) then      select cell as nMOS or pMOS  view  as             symbol(select)

            Now we can place transistor as per your design in schematic view

For placing pins

         create pin or P  ( place vdd, vss and input and output pins

To create a symbol

create -->  cell view  -->  from cell view  -->  OK

in symbol generation options place the pins accordingly (left: in, top: vdd,  bottom: vss, right: out)  -->  ok

In symbol editing click on check and save  (It creates symbol)

To create a test bench

library manager  -->  new  --> cell view

in new file  specify cell name as inverter_test  --> ok

in schematic_editing

add instance  -->  myDesignLib  under cell select inverter and under view symbol(if you want to modify the symbol representation modify)

Apply Vin Vout  Vdd = 1.8V and Gnd

a) For Vdd

Create --> Instance  --> browse for analogLib  --> cell as  Vdc  -->  view as symbol  --> vdc = 1.8  

b) For Vin

Create --> Instance  --> browse for analogLib  --> cell as  Vpulse  -->  view as symbol  -->

            v1 = 0, v2 = 1.8v,

            period = 40n,

            delay = 0n,

            rise time = 100p,  fall time = 100p, 

            pulse width = 20n  --> ok

c) For Vss

            Create --> Instance  --> browse for analogLib  --> cell as  Vdc  -->  view as symbol  -->       vdc = 1.8  

connect vin, vdd, vss, pin to output node

then check and save

  

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For simulating the schematic

Launch  -->  ADE L

Choose analysis option (right side) or under analyses tab select choose

select tran option  in ADE L

set stop time as 100n

select dc option  in ADE L

enable save DC operating point

Under sweep variable enable component parameter then click select component   

then click on input and output wires

under sweep range enabel start-stop

give start 0 and stop 1.8  -->  OK 

In ADE L, select setupoutput option (or) under output tab setup

In setting output, select input and output wires (from design)

In ADE L, select netlist and run option (or) under simulation tab select netlist and run