************************************************************************************
Design of a 4- bit
shift register of Serial- in Serial –out, Serial in parallel out, Parallel in
Serial out and Parallel
in Parallel Out.
(i)
SIPO
module sipo(CLK,
RST_L, SIN, QA, QB, QC, QD);
input CLK, RST_L, SIN;
output QA, QB, QC, QD;
reg QA, QB, QC, QD;
always@(posedge CLK)
begin
if (!RST_L)
{ QA, QB,
QC, QD } <= 4’b0000;
else
begin
QA <=
SIN;
QB <= QA;
QC <= QB;
QD <= QC;
end
end
endmodule
Test
Bench
module tb_sipo;
reg CLK, RST_L, SIN;
wire QA, QB, QC, QD;
sipo
DUT(CLK, RST_L, SIN, QA, QB, QC, QD);
initial
begin
CLK = 0;
RST_L = 0;
#5 RST_L = 1;
end
always
#2
CLK = ! CLK;
always
#5
SIN = !SIN;
endmodule
(ii)
SISO
module siso(CLK,
RST_L, SIN, QOUT);
input CLK, RST_L, SIN;
output QOUT;
reg QOUT;
reg QA=0, QB=0, QC=0, QD=0;
always@(posedge CLK)
begin
if (!RST_L)
begin
{QA, QB, QC,
QD} <= 4’b0000;
QOUT = 0;
end
else
begin
QA <=
SIN;
QB <= QA;
QC <= QB;
QD <= QC;
End
QOUT = QD;
end
endmodule
Test
Bench
module tb_siso;
reg CLK, RST_L, SIN;
wire QOUT;
siso
DUT(CLK, RST_L, SIN, QOUT); -- change instance name to test other modules
initial
begin
CLK = 0;
SIN = 0;
RST_L = 0;
#5 RST_L = 1;
end
always
#2
CLK = ! CLK;
always
#5
SIN = !SIN;
endmodule
***********************************************************************************
(iii)
PIPO
module pipo(CLK,
RST_L, LOAD, SINA, SINB, SINC, SIND, QA, QB, QC, QD);
input CLK, RST_L, LOAD, SINA, SINB,
SINC, SIND;
output QA, QB, QC, QD;
reg QA, QB, QC, QD;
always @ (posedge CLK)
begin
if (!RST_L)
{QA, QB, QC,
QD} = 4’b0000;
else if (LOAD)
begin
QA <=
SINA;
QB <= SINB;
QC <= SINC;
QD <= SIND;
end
else
begin
QA <=
SIN;
QB <= QA;
QC <= QB;
QD <= QC;
end
end
endmodule
test bench
module tb_pipo;
reg CLK, RST_L, LOAD, SINA, SINB,
SINC, SIND;
wire QA, QB, QC, QD;
pipo
DUT(CLK, RST_L, LOAD, SINA, SINB, SINC, SIND, QA, QB, QC, QD);
initial
begin
CLK = 0;
SINA = 0;
SINB = 0;
SINC = 0;
SIND = 0;
RST_L = 0;
#5 RST_L = 1;
end
always
#2
CLK = ! CLK;
always
begin
#1 SINA = ! SINA;
#2
SINB = ! SINB;
#3
SINC = ! SINC;
#4
SIND = ! SIND;
end
endmodule
(iv)
PISO
module piso(CLK,
RST_L, LOAD, SINA, SINB, SINC, SIND, QOUT);
input CLK, RST_L, LOAD, SINA, SINB,
SINC, SIND;
output QOUT;
reg QA, QB, QC, QD, QOUT;
always @ (posedge CLK)
begin
if (!RST_L)
{QA, QB, QC,
QD} <= 4’b0000;
else if (LOAD)
begin
QA <=
SINA;
QB <= SINB;
QC <= SINC;
QD <= SIND;
end
else
begin
QA <=
SIN;
QB <= QA;
QC <= QB;
QD <= QC;
end
QOUT <=
QD;
end
endmodule
TEST BENCH
module tb_piso;
reg CLK, RST_L, LOAD, SINA, SINB,
SINC, SIND;
wire
QOUT;
piso
u0(CLK, RST_L, LOAD, SINA, SINB, SINC, SIND, QOUT);
--
Change the module instance name as per the module to test
initial
begin
CLK = 0;
SINA = 0;
SINB = 0;
SINC = 0;
SIND = 0;
RST_L = 0;
#5 RST_L = 1;
end
always
#2
CLK = ! CLK;
always
begin
#1 SINA =
! SINA;
#2
SINB = ! SINB;
#3
SINC = ! SINC;
#4
SIND = ! SIND;
end
endmodule
************************************************************************************ 
No comments:
Post a Comment