Verilog_program_for_binary_to_gray_converter_data_flow_model

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Design of 4 bit binary to gray code converter - Data Flow Model

Verilog Module

module bin2gray(B, G);

      input [3:0]B;

      output [3:0]G;

            assign  G[0] =  B[1] ^ B[0];

            assign  G[1] =  B[2] ^ B[1];;

            assign  G[2] =  B[3] ^ B[2];;

            assign  G[3] =  B[3];

endmodule

Test Bench

module tb_bin2gray;

      reg [3:0]B;

      wire [3:0]G;

            bin2gray DUT(B, G);

            initial

                 begin

                          B = 4’b0000;

 #100 $stop;

     end

            always  #5  B = B + 4’b0001;

endmodule

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