74x139 Behavioral model using simple signal assignment statement

74x139     Behavioral model using simple signal assignment statement

library IEEE;

use IEEE.std_logic_1164.all;

entity dec74x139 is

port ( G_L    :        in       STD_LOGIC;

                    A, B    :        in       STD_LOGIC;

                    Y0_L, Y1_L, Y2_L, Y3_L:           out     STD_LOGIC);

end dec74x139;

architecture arch5 of dec74x139 is

begin

     process ( G_L, A, B)  

     begin

 Y0_L <=  (not G_L) nand (not A) nand (not B);

          Y1_L <=  (not G_L) nand (not A) nand B;

          Y2_L <=  (not G_L) nand A nand (not B);

          Y3_L <=  (not G_L) nand A nand B;

     end process;

end arch5;