74x139 Using structural design model

74x139     Using structural design model

library IEEE;

use IEEE.std_logic_1164.all;

entity dec74x139 is

port ( G_L: in  STD_LOGIC;

                    A, B: in  STD_LOGIC;

                   Y0_L, Y1_L, Y2_L, Y3_L: out  STD_LOGIC);

end dec74x139;

architecture arch4 of dec74x139 is

          signal G, X1, X2 : std_logic;

          component not_gate ( I : in std_logic; O: out std_logic);

          end component;

          component nand_gate(I3, I2, I1: in std_logic; O:out std_logic);

          end component;

begin

          U0:    not_gate     port map (G_L, G);

          U1:    not_gate     port map (A, X1);

          U2:    not_gate     port map (B, X2);

          U3:    nand_gate   port map (G, X1, X2, Y0_L);

          U4:    nand_gate   port map (G, X1, B, Y1_L);

          U5:    nand_gate   port map (G, A, X2, Y2_L);

          U6:    nand_gate   port map (G, A, B, Y3_L);

end arch4;