VHDL Program for Realization of 4x1 multiplexer using 2x1
Multiplexer
library IEEE;
use
IEEE.std_logic_1164.all;
entity mux_4x1_using_2x1
is
port( I3, I2, I1, I0: in
std_logic;
S1, S0 : in std_logic;
Y: out std_logic);
end mux_4x1_using_2x1;
architecture arch1
of mux_4x1_using_2x1 is
component mux2x1 port (I1, I0, S: in
std_logic; Y: out std_logic); end component;
signal x1, x2 : std_logic;
begin
u0:
mux2x1 port map (I1, I0, S0, x1);
u1: mux2x1 port map (I3, I2, S0, x2);
u2:
mux2x1 port map (x2, x1, S1, Y);
end arch1;
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