VHDL Program for 256*8 RAM

Library  ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Entity ram256*8 is port

(address: in std_logic_vector(7 downto 0);

 data: inout std_logic_vector(7 downto 0);

 read : in std_logic

 write : in std_logic);

end ram256*8;

architecture arch_ram of ram256x8 is

            type ram_type is array (0 to 255) of std_logic_vector(7

                   downto 0);

            signal ram1: ram_type:= (others => ( others => ’0’));

begin

process

begin

if (write = ‘1’) then

ram1(conv_integer(address) <= data;

elsif (read = ‘1’) then

data <= ram1(conv_integer(address));

else

data <= (others => ‘Z’);

end if;

end process;

end simple_ram;