Electrical Behavior of CMOS Circuits

Electrical Behavior of CMOS Circuits

1. Logic voltage levels: - CMOS devices operating under normal conditions are guaranteed to produce output voltage levels within well-defined LOW and HIGH ranges.
2. DC noise margins:- Nonnegative DC noise margins ensure that the highest LOW  voltage produced by an output is always lower than the highest voltage that an input can reliably interpret as LOW, and that the lowest HIGH voltage produced by an output is always higher than the lowest voltage that an input can reliably interpret as HIGH.
3. Fanout: - This refers to the number and type of inputs that are connected to a given output. Fanout affect the speed at which the output changes from one state to another.
4. Speed: - The time that it takes a CMOS output to change from the LOW state to the HIGH state, or vice versa. It depends on both the internal structure of the device and the characteristics of the other devices that it drives.
5. Power consumption: - The power consumed by a CMOS device depends on its internal structure, the input signals that it receives, the other devices that it drives, and how often its output changes between LOW and HIGH.
6. Noise :- Noise can be generated by a number of sources:

–        Cosmic rays

–        Magnetic fields from nearby machinery

–        Power-supply disturbances

–        The switching action of the logic circuits them selves.

7. Electrostatic discharge: - CMOS devices can be destroyed just by touching it.
8. Open-drain outputs: - Some CMOS outputs omit the usual p-channel pull-up transistors. In the HIGH state, such outputs are effectively a “no-connection,” which is useful in some applications.
9. Three-state outputs: - Some CMOS devices have an extra “output enable” control input that can be used to disable both the p-channel pull-up transistors and the n-channel pull-down transistors.