74x138 Behavioral model using if – else statement
library IEEE;
use IEEE.std_logic_1164.all;
entity dec74x138 is
port ( G1, G2A_L, G2B_L : in STD_LOGIC;
A, B, C : in STD_LOGIC;
Y0_L, Y1_L, Y2_L, Y3_L, Y4_L, Y5_L,
Y6_L, Y7_L: out STD_LOGIC);
end dec74x138;
architecture arch6 of dec74x138 is
begin
process (G1, G2A_L, G2B_L, A, B, C)
begin
Y0_L <= ‘1’;
Y1_L <= ‘1’; Y2_L <= ‘1’; Y3_L <=
‘1’;
Y4_L <= ‘1’;
Y5_L <= ‘1’; Y6_L <= ‘1’; Y7_L <=
‘1’;
if G1 & G2A_l & G2B_L = “100” then
if A & B
& C = “000” then Y0_L <= ‘0’;
elsif
A & B & C = “001” then Y1_L <= ‘0’;
elsif A & B & C = “010” then Y2_L
<= ‘0’;
elsif G_L & A & B = “011” then Y3_L
<= ‘0’;
elsif G_L
& A & B = “100” then Y4_L <= ‘0’;
elsif G_L
& A & B = “101” then Y5_L <= ‘0’;
elsif G_L
& A & B = “110” then Y6_L <= ‘0’;
elsif G_L
& A & B = “111” then Y7_L <= ‘0’;
end if;
end if;
end process;
end arch6;
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