Verilog_program_for_binary_to_gray_code_converter_behavioral_Model

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Design of 4 bit binary to gray code converter - Behavioral Model

Verilog Module

  BEHAVIORAL MODEL USING SIMPLE ASSIGNMENT STATEMENT

module bin2gray(B, G);

      input [3:0]B;

      output [3:0]G;

      reg [3:0]G;

            always@(B)

            begin

G[0] =  B[1] ^ B[0];

                         G[1] =   B[2] ^ B[1];

                         G[2] =   B[3] ^ B[2];

                         G[3] =   B[3];

            end

endmodule

 BEHAVIORAL MODEL USING CASE STATEMENT

module bin2gray(B, G);

      input [3:0]B;

      output [3:0]G;

      reg [3:0]G;

            always@(B)

            begin 
                        case (B)

                                    4’b0000 :         G = 4’b0000;

                                    4’b0001 :         G = 4’b0001;

                                    4’b0010 :         G = 4’b0011;

                                    4’b0011 :         G = 4’b0010;
                                    4’b0100 :         G = 4’b0110;
                                    4’b0101 :         G = 4’b0111;

                                    4’b0110 :         G = 4’b0101;

                                    4’b0111 :         G = 4’b0100;
                                    4’b1000 :         G = 4’b1100;
                                    4’b1001 :         G = 4’b1101;

                                    4’b1010 :         G = 4’b1111;

                                    4’b1011 :         G = 4’b1110;
                                    4’b1100 :         G = 4’b1010;
                                    4’b1101 :         G = 4’b1011;

                                    4’b1110 :         G = 4’b1001;

                                    4’b1111 :         G = 4’b1000;
                                   default:            G = 4’b0000;

endcase

            end

endmodule

  BEHAVIORAL MODEL USING IF STATEMENT

module bin2gray(B, G);

      input [3:0]B;

      output [3:0]G;

      reg [3:0]G;

            always@(B)

            begin

                        if  (B[1] ^ B[0])          G[0] = 1;          else      G[0] = 0;

                        if (B[2] ^ B[1])            G[1] = 1;          else      G[1] = 0;

                        if (B[3] ^ B[2])            G[2] = 1;          else      G[2] = 0;

                        if (B[3])                         G[3] = 1;          else      G[3] = 0; 
            end

endmodule

 BEHAVIORAL MODEL USING IF STATEMENT

module bin2gray(B, G);

      input [3:0]B;

      output [3:0]G;

      reg [3:0]G;

            always@(B)

            begin

                        if (B == 4’b0000)                   G = 4’b0000;

else if (B == 4’b0001)           G = 4’b0001;

                        else if (B == 4’b0010)            G = 4’b0011;

else if (B == 4’b0011)            G = 4’b0010;

else if (B == 4’b0100)           G = 4’b0110;

else if (B == 4’b0101)            G = 4’b0111;                                                               
else if (B == 4’b0110)             G = 4’b0101;
else if (B == 4’b0111)             G = 4’b0100;

                        else if (B == 4’b1000)           G = 4’b1100;

else if (B == 4’b1001)           G = 4’b1101;

                        else if (B == 4’b1010)            G = 4’b1111;

else if (B == 4’b1011)            G = 4’b1110;

else if (B == 4’b1100)           G = 4’b1010;

else if (B == 4’b1101)            G = 4’b1011;

                        else if (B == 4’b1110)             G = 4’b1001;

else if (B == 4’b1111)             G = 4’b1000;

else                                           G = 4’b0000;

            end 
endmodule

Test Bench

module tb_bin2gray;

      reg [3:0]B;

      wire [3:0]G;

            bin2gray DUT(B, G);

            initial

                 begin

                          B = 4’b0000;

 #100 $stop;

     end

            always  #5  B = B + 4’b0001;

endmodule

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