Verilog_Module_for_8to3_priority_encoder

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Design of 8-to-3 Priority encoder

Behavioral model using case statement

module priorityenc(I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;

always@( I)

                casex(I)

                                7’b1???????:    Y = 3’b111;

                                7’b?1??????:    Y = 3’b110;

                                7’b??1?????:    Y = 3’b101;

                                7’b???1????:    Y = 3’b100;

                                7’b????1???:    Y = 3’b011;

                                7’b?????1??:    Y = 3’b010;

                                7’b??????1?:    Y = 3’b001;

                                7’b???????1:    Y = 3’b000;

                                default : begin

                                                                       Y = 3’b000;

                                                           $display(“error”);

                                                 end

                 endcase

endmodule

Behavioral model using if statement

module priorityenc(I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;

always@( I)

                if(I[7])                   Y = 3’b111;

                else if(I[6])          Y = 3’b110;

                else if(I[5])          Y = 3’b101;

                else if(I[4])          Y = 3’b100;

                else if(I[3])          Y = 3’b011;

                else if(I[2])          Y = 3’b010;

                else if(I[1])          Y = 3’b001;

                else if(I[0])          Y = 3’b000;

                else        begin

Y = 3’b000;

                                                $display(“error”);

                                  end

endmodule

Testbench

module tb_priorityenc;

reg [7:0]I;

wire [7:0]Y;

            priorityenc DUT(I, Y);

                                intial

                                begin

                                                I = 8’b00000000

                                                #100     $stop;

                                end

                                always                  #3    I = I + 1;

endmodule

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