74x138 Using simple signal assignment statement in data flow model

74x138     Using simple signal assignment statement in data flow model

library IEEE;

use IEEE.std_logic_1164.all;

entity dec74x138 is

port ( G1, G2A_L, G2B_L : in  STD_LOGIC;

                    A, B, C : in   STD_LOGIC;

                    Y0_L, Y1_L, Y2_L, Y3_L, Y4_L, Y5_L, Y6_L, Y7_L:  out  STD_LOGIC);

end dec74x138;

architecture arch1 of dec74x138 is

begin

          Y0_L <= G1 nand (not G2A_L) nand (not G2B_L) nand (not A) nand (not B) nand (not C);

          Y1_L <= G1 nand (not G2A_L) nand (not G2B_L) nand (not A) nand (not B) nand C;

          Y2_L <= G1 nand (not G2A_L) nand (not G2B_L) nand (not A) nand B nand (not C);

          Y3_L <= G1 nand (not G2A_L) nand (not G2B_L) nand (not A) nand B nand C;

 Y4_L <= G1 nand (not G2A_L) nand (not G2B_L) nand A nand (not B) nand (not C);

          Y5_L <= G1 nand (not G2A_L) nand (not G2B_L) nand A nand (not B) nand C;

          Y6_L <= G1 nand (not G2A_L) nand (not G2B_L) nand A nand B nand (not C);

          Y7_L <= G1 nand (not G2A_L) nand (not G2B_L) nand A nand B nand C;

end arch1;