74X138 Using structural design model

74X138     Using structural design model

library IEEE;

use IEEE.std_logic_1164.all;

entity dec74x138 is

port ( G1, G2A_L, G2B_L : in  STD_LOGIC;

                   A, B, C : in   STD_LOGIC;

                   Y0_L, Y1_L, Y2_L, Y3_L, Y4_L, Y5_L, Y6_L, Y7_L:  out  STD_LOGIC);

end dec74x138;

architecture arch4 of dec74x138 is

          signal G2A, G2B, EN, X1, X2, X3 : std_logic;

          component not_gate ( I : in std_logic; O: out std_logic);

          end component;

          component nand3_gate(I3, I2, I1: in std_logic; O:out std_logic);

          end component;

component nand4_gate(I4, I3, I2, I1: in std_logic; O:out std_logic);

          end component;

begin

          U0: not_gate  port map (G2A_L, G2A);

          U1: not_gate  port map (G2B_L, G2B);

          U2: not_gate  port map (A, X1);

          U3: not_gate  port map (B, X2);

          U4: not_gate  port map (C, X3);

          U5: nand3_gate  port map (G1, G2A, G2B, EN);

          U6: nand4_gate  port map (EN, X1, X2, X3, Y0_L);

          U7: nand4_gate  port map (EN, X1, X2, C, Y1_L);

          U8: nand4_gate  port map (EN, X1, B, X3, Y2_L);

          U9: nand4_gate  port map (EN, X1, B, C, Y3_L);

          U10: nand4_gate   port map (EN, A, X2, X3, Y4_L);

          U11: nand4_gate   port map (EN, A, X2, C, Y5_L);

          U12: nand4_gate   port map (EN, A, B, X3, Y6_L);

          U13: nand4_gate   port map (EN, A, B, C, Y7_L);

end arch4;